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mcm63z836 ? mcm63z918 1 motorola fast sram product proposal 256k x 36 and 512k x 18 bit pipelined zbt ? ram synchronous fast static ram the zbt ram is an 8mbit synchronous fast static ram designed to provide zero bus turnaround ? . the zbt ram allows 100% use of bus cycles during backtoback read/write and write/read cycles. the mcm63z836 (organized as 256k words by 36 bits) and the mcm63z918 (organized as 512k words by 18 bits) are fabricated in motorola's high performance silicon gate cmos tech- nology. this device integrates input registers, an output register, a 2bit address counter, and high speed sram onto a single monolithic circuit for reduced parts count in communication applications. synchronous design allows precise cycle control with the use of an external positiveedgetriggered clock (ck). cmos circuitry reduces the overall power consumption of the integrated functions for greater reliability. addresses (sa), data inputs (dq), and all control signals except output enable (g ), sleep mode (zz), and linear burst order (lbo ) are clock (ck) controlled through positiveedgetriggered noninverting registers. write cycles are internally selftimed and are initiated by the rising edge of the clock (ck) input. this feature eliminates complex offchip write pulse generation and provides increased timing flexibility for incoming signals. for read cycles, pipelined sram output data is temporarily stored by an edge triggered output register and then released to the output buffers at the next rising edge of clock (ck). ? 3.3 v core, 3.3 v lvttl and lvcmos compatible i/o supply ? mcm63z836 / 918225 = 2.6 ns access / 4.4 ns cycle (225 mhz) mcm63z836 / 918200 = 3.2 ns access / 5 ns cycle (200 mhz) mcm63z836 / 918166 = 3.6 ns access / 6 ns cycle (166 mhz) ? selectable burst sequencing order (linear/interleaved) ? internally selftimed write cycle ? sleep mode (zz) ? twocycle deselect ? byte write control ? adv controlled burst ? ieee 11491 sample only jtag ? 100pin tqfp and 119bump pbga packages zbt and zero bus turnaround are trademarks of integrated device technology, inc., and the architecture is supported by micron technology, inc. and motorola, inc. this document contains information on a new product under development. motorola reserves the right to change or discontinue this product without notice. order this document by mcm63z836/d semiconductor technical data mcm63z836 mcm63z918 tq package tqfp case 983a01 zp package pbga case 99902 rev 1 6/2/99 ? motorola, inc. 1999
mcm63z836 ? mcm63z918 2 motorola fast sram burst address counter g sbx se3 dataout register datain register memory array se2 lbo ck cke sw se1 datain register write address register write address register control logic sa dq adv zz 36 or 18 k k k address register control register control logic logic block diagram k
mcm63z836 ? mcm63z918 3 motorola fast sram mcm63z836 pin assignments 6 5 4 3 2 17 b c v ss g a d e f h j v ss v ss sbb v ss sa v ss v ss v ss sa sa sa sa sa sa sa sa nc sa sa nc nc nc dqb sa sa trst zz cke dqa dqa v ddq v ddq dqb v ddq dqb dqb dqa dqa v dd v dd tdo sa tdi tms nc tck dqd dqd v ss sa0 nc lbo dqa dqa sa1 v ss dqd dqd v ddq dqd v ss v dd dqa dqa sba sbd dqd dqd dqd dqd v ss ck v ss dqc dqa v dd nc v dd nc v dd v ddq dqc v ss sw dqb dqb dqb sa sbc dqc dqc v ddq dqc v ss g dqb se1 v ss dqc dqc dqc dqc v ss nc dqb v dd nc nc se2 sa adv nc k l m n p r t u v ddq v ddq se3 v ddq v ddq nc 119bump pgba top view not to scale v ss v ddq 37 38 34 35 36 42 43 39 40 41 45 46 44 31 32 33 50 49 48 47 94 93 97 96 95 89 88 92 91 90 86 85 87 100 99 98 81 82 83 84 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 dqb dqb dqb 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dqb dqb v ddq v ss dqc dqc dqc v ss dqd dqd dqd dqd nc nc sa sa sa sa sa sa sa lbo nc nc v ddq v ss dqa dqa dqa dqb dqb dqb dqb zz dqa dqa v ss v dd v dd dqa dqa dqa dqa v ss v ddq v ddq v ss dqc dqc dqc dqc v ddq v ss v ss v ddq dqd dqd dqc dqc v dd v dd v dd dqd dqd dqd v ss v ddq v dd v ss sbd sbc sbb sba se3 g se1 se2 sa sa sa sa sa sa sa sa sa1 sa0 v dd v ss ck sa cke nc adv sw 100pin tqfp top view
mcm63z836 ? mcm63z918 4 motorola fast sram mcm63z836 tqfp pin descriptions pin locations symbol type description 85 adv input synchronous load /advance: loads a new address into counter when low. ram uses internally generated burst addresses when high. 89 ck input clock: this signal registers the address, data in, and all control signals except g and lbo . 87 cke input clock enable: disables the ck input when cke is high. (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79, 80 (c) 1, 2, 3, 6, 7, 8, 9, 12, 13 (d) 18, 19, 22, 23, 24, 25, 28, 29, 30 dqx i/o synchronous data i/o: axo refers to the byte being read or written (byte a, b, c, d). 86 g input asynchronous output enable. 31 lbo input linear burst order input: this pin must remain in steady state (this signal not registered or latched). it must be tied high or low. low e linear burst counter. high e interleaved burst counter. 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 81, 82, 83, 99, 100 sa input synchronous address inputs: these inputs are registered and must meet setup and hold times. 37, 36 sa0, sa1 input synchronous burst address inputs: the two lsbs of the address field. these pins must preset the burst address counter values. these inputs are registered and must meet setup and hold times. 93, 94, 95, 96 (a) (b) (c) (d) sbx input synchronous byte write inputs: enables write to byte axo (byte a, b, c, d) in conjunction with sw . has no effect on read cycles. 98 se1 input synchronous chip enable: active low to enable chip. 97 se2 input synchronous chip enable: active high for depth expansion. 92 se3 input synchronous chip enable: active low for depth expansion. 88 sw input synchronous write: this signal writes only those bytes that have been selected using the byte write sbx pins. 64 zz input sleep mode: this active high asynchronous signal places the ram into the lowest power mode. the zz pin disables the rams internal clock when placed in this mode. when zz is negated, the ram remains in low power mode until it is commanded to read or write. data integrity is maintained upon returning to normal operation. 14, 15, 16, 41, 65, 66, 91 v dd supply core power supply. 4, 11, 20, 27, 54, 61, 70, 77 v ddq supply i/o power supply. 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 v ss supply ground. 38, 39, 42, 43, 84 nc e no connection: there is no connection to the chip.
mcm63z836 ? mcm63z918 5 motorola fast sram mcm63z836 pbga pin descriptions pin locations symbol type description 4b adv input synchronous load /advance: loads a new address into counter when low. ram uses internally generated burst addresses when high. 4k ck input clock: this signal registers the address, data in, and all control signals except g and lbo . 4m cke input clock enable: disables the ck input when cke is high. (a) 6k, 7k, 6l, 7l, 6m, 6n, 7n, 6p, 7p (b) 6d, 7d, 6e, 7e, 6f, 6g, 7g, 6h, 7h (c) 1d, 2d, 1e, 2e, 2f, 1g, 2g, 1h, 2h (d) 1k, 2k, 1l, 2l, 2m, 1n, 2n, 1p, 2p dqx i/o synchronous data i/o: axo refers to the byte being read or written (byte a, b, c, d). 4f g input asynchronous output enable. 3r lbo input linear burst order input: this pin must remain in steady state (this signal not registered or latched). it must be tied high or low. low e linear burst counter. high e interleaved burst counter. 2a, 3a, 5a, 6a, 3b, 5b, 2c, 3c, 5c, 6c, 4g, 2r, 6r, 3t, 4t, 5t sa input synchronous address inputs: these inputs are registered and must meet setup and hold times. 4n, 4p sa1, sa0 input synchronous burst address inputs: the two lsbs of the address field. these pins must preset the burst address counter values. these inputs are registered and must meet setup and hold times. 5l, 5g, 3g, 3l (a) (b) (c) (d) sbx input synchronous byte write inputs: enables write to byte axo (byte a, b, c, d) in conjunction with sw . has no effect on read cycles. 4e se1 input synchronous chip enable: active low to enable chip. 2b se2 input synchronous chip enable: active high for depth expansion. 6b se3 input synchronous chip enable: active low for depth expansion. 4h sw input synchronous write: this signal writes only those bytes that have been selected using the byte write sbx pins. 4u tck input boundary scan pin, test clock: if boundary scan is not used, tck must be tied to v dd or v ss . 3u tdi input boundary scan pin, test data in. 5u tdo output boundary scan pin, test data out. 2u tms input boundary scan pin, test mode select. 6u trst input boundary scan pin, asynchronous test reset. if boundary scan is not used, trst must be tied to v ss . 7t zz input sleep mode: this active high asynchronous signal places the ram into the lowest power mode. the zz pin disables the rams internal clock when placed in this mode. when zz is negated, the ram remains in low power mode until it is commanded to read or write. data integrity is maintained upon returning to normal operation. 4c, 2j, 4j, 6j, 1r, 4r, 5r v dd supply core power supply. 1a, 7a, 1f, 7f, 1j, 7j, 1m, 7m, 1u, 7u v ddq supply i/o power supply. 3d, 5d, 3e, 5e, 3f, 5f, 3h, 5h, 3k, 5k, 3l, 3m, 5m, 3n, 5n, 3p, 5p v ss supply ground. 4a, 1b, 7b, 1c, 7c, 4d, 3j, 5j, 7r, 1t, 2t, 6t nc e no connection: there is no connection to the chip.
mcm63z836 ? mcm63z918 6 motorola fast sram mcm63z918 pin assignments 6 5 4 3 2 17 v ss v ss v ss v ss v ss sa v ss v ss v ss sa sa sa sa sa sa sa sa sa sa sa sa nc nc nc sa sa trst zz cke nc nc v ddq v ddq nc v ddq dqa dqa dqa dqa v dd v dd tdo nc tdi tms nc tck nc dqb v ss sa0 nc lbo nc dqa sa1 v ss nc dqb v ddq dqb v ss v dd nc dqa sba v ss nc dqb nc dqb v ss ck v ss dqb nc v dd nc v dd nc v dd v ddq nc v ss sw dqa dqa nc sa sbb dqb nc v ddq nc v ss g nc se1 v ss dqb nc dqb nc v ss nc dqa v dd nc nc se2 sa adv nc not to scale v ddq v ddq se3 v ddq v ddq nc b c g a d e f h j k l m n p r t u 119bump pgba top view v ss v ddq 37 38 34 35 36 42 43 39 40 41 45 46 44 31 32 33 50 49 48 47 94 93 97 96 95 89 88 92 91 90 86 85 87 100 99 98 81 82 83 84 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 sa nc nc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dqa dqa v ddq v ss nc nc nc v ss dqb dqb dqb nc nc nc sa sa sa sa sa sa sa lbo nc nc v ddq v ss nc nc nc nc dqa dqa dqa dqa dqa v ss v dd v dd zz dqa dqa nc nc v ss v ddq v ddq v ss nc nc dqb dqb v ddq v ss v ss v ddq dqb dqb dqb dqb v dd v dd v dd nc nc nc v ss v ddq v dd v ss nc nc sbb sba se3 se1 se2 sa sa sa sa sa sa sa1 sa0 v dd v ss ck 100pin tqfp top view g sa sa sa cke nc adv sw
mcm63z836 ? mcm63z918 7 motorola fast sram mcm63z918 tqfp pin descriptions pin locations symbol type description 85 adv input synchronous load /advance: loads a new address into counter when low. ram uses internally generated burst addresses when high. 89 ck input clock: this signal registers the address, data in, and all control signals except g and lbo . 87 cke input clock enable: disables the ck input when cke is high. (a) 58, 59, 62, 63, 68, 69, 72, 73, 74 (b) 8, 9, 12, 13, 18, 19, 22, 23, 24 dqx i/o synchronous data i/o: axo refers to the byte being read or written (byte a, b). 86 g input asynchronous output enable. 31 lbo input linear burst order input: this pin must remain in steady state (this signal not registered or latched). it must be tied high or low. low e linear burst counter. high e interleaved burst counter. 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 80, 81, 82, 83, 99, 100 sa input synchronous address inputs: these inputs are registered and must meet setup and hold times. 37, 36 sa0, sa1 input synchronous burst address inputs: the two lsbs of the address field. these pins must preset the burst address counter values. these inputs are registered and must meet setup and hold times. 93, 94 (a) (b) sbx input synchronous byte write inputs: enables write to byte axo (byte a, b) in conjunction with sw . has no effect on read cycles. 98 se1 input synchronous chip enable: active low to enable chip. 97 se2 input synchronous chip enable: active high for depth expansion. 92 se3 input synchronous chip enable: active low for depth expansion. 88 sw input synchronous write: this signal writes only those bytes that have been selected using the byte write sbx pins. 64 zz input sleep mode: this active high asynchronous signal places the ram into the lowest power mode. the zz pin disables the rams internal clock when placed in this mode. when zz is negated, the ram remains in low power mode until it is commanded to read or write. data integrity is maintained upon returning to normal operation. 14, 15, 16, 41, 65, 66, 91 v dd supply core power supply. 4, 11, 20, 27, 54, 61, 70, 77 v ddq supply i/o power supply. 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 v ss supply ground. 1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 43, 51, 52, 53, 56, 57, 75, 78, 79, 84, 95, 96 nc e no connection: there is no connection to the chip.
mcm63z836 ? mcm63z918 8 motorola fast sram mcm63z918 pbga pin descriptions pin locations symbol type description 4b adv input synchronous load /advance: loads a new address into counter when low. ram uses internally generated burst addresses when high. 4k ck input clock: this signal registers the address, data in, and all control signals except g and lbo . 4m cke input clock enable: disables the ck input when cke is high. (a) 6d, 7e, 6f, 7g, 6h, 7k, 6l, 6n, 7p (b) 1d, 2e, 2g, 1h, 2k, 1l, 2m, 1n, 2p dqx i/o synchronous data i/o: axo refers to the byte being read or written (byte a, b). 4f g input asynchronous output enable. 3r lbo input linear burst order input: this pin must remain in steady state (this signal not registered or latched). it must be tied high or low. low e linear burst counter. high e interleaved burst counter. 2a, 3a, 5a, 6a, 3b, 5b, 2c, 3c, 5c, 6c, 4g, 2r, 6r, 2t, 3t, 5t, 6t sa input synchronous address inputs: these inputs are registered and must meet setup and hold times. 4n, 4p sa1, sa0 input synchronous address inputs: these pins must be wired to the two lsbs of the address bus for proper burst operation. these inputs are registered and must meet setup and hold times. 5l, 3g (a) (b) sbx input synchronous byte write inputs: enables write to byte axo (byte a, b) in conjunction with sw . has no effect on read cycles. 4e se1 input synchronous chip enable: active low to enable chip. 2b se2 input synchronous chip enable: active high for depth expansion. 6b se3 input synchronous chip enable: active low for depth expansion. 4h sw input synchronous write: this signal writes only those bytes that have been selected using the byte write sbx pins. 4u tck input boundary scan pin, test clock: if boundary scan is not used, tck must be tied to v dd or v ss . 3u tdi input boundary scan pin, test data in. 5u tdo output boundary scan pin, test data out. 2u tms input boundary scan pin, test mode select. 6u trst input boundary scan pin, asynchronous test reset. if boundary scan is not used, trst must be tied to v ss . 7t zz input sleep mode: this active high asynchronous signal places the ram into the lowest power mode. the zz pin disables the rams internal clock when placed in this mode. when zz is negated, the ram remains in low power mode until it is commanded to read or write. data integrity is maintained upon returning to normal operation. 4c, 2j, 4j, 6j, 1r, 4r, 5r v dd supply core power supply. 1a, 7a, 1f, 7f, 1j, 7j, 1m, 7m, 1u, 7u v ddq supply i/o power supply. 3d, 5d, 3e, 5e, 3f, 5f, 5g, 3h, 5h, 3k, 5k, 3l, 3m, 5m, 3n, 5n, 3p, 5p v ss supply ground. 4a, 1b, 7b, 1c, 7c, 2d, 4d, 7d, 1e, 6e, 2f, 1g, 6g, 2h, 7h, 3j, 5j, 1k, 6k, 2l, 4l, 7l, 6m, 2n, 7n, 1p, 6p, 7r, 1t, 4t nc e no connection: there is no connection to the chip.
mcm63z836 ? mcm63z918 9 motorola fast sram truth table ck cke e sw sbx adv sa0 sax next operation input command code notes lh 1 x x x x x hold h 1, 2 lh 0 false x x 0 x deselect d 1, 2 lh 0 true 0 v 0 v load address, new write w 1, 2, 3, 4, 5 lh 0 true 1 x 0 v load address, new read r 1, 2 lh 0 x x v (w) 1 x burst b 1, 2, 4, 67 x (r, d) continue 6, 7 notes: 1. x = don`t care, 1 = logic high, 0 = logic low, v = valid signal, according to ac operating conditions and characteristics. 2. e = true if se1 and se3 = 0, and se2 = 1. 3. byte write enables, sbx are evaluated only as new write addresses are loaded. 4. no control inputs except cke , sbx , and adv are recognized in a clock cycle where adv is sampled high. 5. a write with sbx not valid does load addresses. 6. a burst write with sbx not valid does increment address. 7. adv controls whether the ram enters burst mode. if the previous cycle was a write, then adv = 1 results in a burst write. if the previous cycle is a read, then adv = 1 results in a burst read. adv = 1 will also continue a deslect cycle. asynchronous truth table operation zz g i/o status read l l data out (dqx) read l h highz write l x highz deselected l x highz sleep h x highz write truth table cycle type sw sba sbb sbc (see note 1) sbd (see note 1) read h x x x x write byte a l l h h h write byte b l h l h h write byte c (see note 1) l h h l h write byte d (see note 1) l h h h l write all bytes l l l l l note: 1. valid only for x36. linear burst address table (lbo = v ss ) 1st address (external) 2nd address (internal) 3rd address (internal) 4th address (internal) x . . . x00 x . . . x01 x . . . x10 x . . . x11 x . . . x01 x . . . x10 x . . . x11 x . . . x00 x . . . x10 x . . . x11 x . . . x00 x . . . x01 x . . . x11 x . . . x00 x . . . x01 x . . . x10 interleaved burst address table (lbo = v dd ) 1st address (external) 2nd address (internal) 3rd address (internal) 4th address (internal) x . . . x00 x . . . x01 x . . . x10 x . . . x11 x . . . x01 x . . . x00 x . . . x11 x . . . x10 x . . . x10 x . . . x11 x . . . x00 x . . . x01 x . . . x11 x . . . x10 x . . . x01 x . . . x00
mcm63z836 ? mcm63z918 10 motorola fast sram input command code and state name definition diagram false e ck cke true true sa0 sax valid valid sw adv valid valid sbx dbw brbh deselect continue deselect new write burst write new read burst read hold input command code note: cycles are named for their control inputs, not for data i/o state.
mcm63z836 ? mcm63z918 11 motorola fast sram figure 1. zbt ram state diagram deselect burst write burst read w r d new write new read b w r w r w b b b r b r d d w d d current state (n) next state (n + 1) transition ? input command code key: notes: 1. input command codes (d, w, r, and b) represent control pin inputs as indicated in the truth table. 2. hold (i.e., cke sampled high) is not shown simply because cke = 1 blocks clock input and therefore, blocks any state change. ck command code state ? dq n n + 1 n + 2 n + 3 current state next state figure 2. state definitions for zbt ram state diagram
mcm63z836 ? mcm63z918 12 motorola fast sram figure 3. data i/o state diagram highz highz (data in) data out (q valid) w r b w current state (n) next state (n + 2) transition ? input command code key: intermediate intermediate intermediate intermediate intermediate b r d d w r intermediate d b notes: 1. input command codes (d, w, r, and b) represent control pin inputs as indicated in the truth table. 2. hold (i.e., cke sampled high) is not shown simply because cke = 1 blocks clock input and therefore, blocks any state change. intermediate state (n + 1) transition ck command code state state name ? dq n n + 1 n + 2 n + 3 current state intermediate state next state figure 4. state definitions for i/o state diagrams
mcm63z836 ? mcm63z918 13 motorola fast sram dc operating conditions and characteristics (v dd = 3.3 v 5%, t a = 0 to 70 c unless otherwise noted) recommended operating conditions and dc characteristics: 2.5 v i/o supply (voltages referenced to v ss = 0 v) parameter symbol min typ max unit supply voltage v dd 3.135 3.3 3.465 v i/o supply voltage v ddq 2.375 2.5 2.9 v input low voltage v il 0.3 e 0.7 v input high voltage v ih 1.7 e v dd + 0.3 v input high voltage i/o pins v ih2 1.7 e v ddq + 0.3 v output low voltage (i ol = 2 ma) v ol e e 0.7 v output high voltage (i ol = 2 ma) v oh 1.7 e e v recommended operating conditions and dc characteristics: 3.3 v i/o supply (voltages referenced to v ss = 0 v) parameter symbol min typ max unit supply voltage v dd 3.135 3.3 3.465 v i/o supply voltage v ddq 3.135 3.3 3.465 v input low voltage v il 0.5 e 0.8 v input high voltage v ih 2 e v dd + 0.5 v input high voltage i/o pins v ih2 2 e v ddq + 0.5 v output low voltage (i ol = 8 ma) v ol e e 0.4 v output high voltage (i oh = 8 ma) v oh 2.4 e e v v ih 20% t khkh (min) v ss v ss 1.0 v figure 5. undershoot voltage
mcm63z836 ? mcm63z918 14 motorola fast sram dc characteristics and supply currents parameter symbol min typ max unit notes input leakage current (0 v v in v dd ) i lkg(i) e e 1 m a 1 output leakage current (0 v v in v ddq ) i lkg(o) e e 1 m a ac supply current (device selected, all outputs open, freq = max) includes supply current for both v dd and v ddq i dda 225 i dda 200 i dda 166 e e e e e e 300 290 280 ma 2, 3, 4 cmos standby supply current (device deselected, freq = 0, v dd = max, v ddq = max, all inputs static at cmos levels) i sb2 e e 10 ma 5, 6 sleep mode supply current (device deselected, freq = max, v dd = max, all other inputs static at cmos levels, zz v dd 0.2 v) i zz e e tbd ma 1, 5, 6 clock running (device deselected, freq = max, v dd = max, all inputs toggling at cmos levels) i sb4 225 i sb4 200 i sb4 166 e e e e e e 100 100 90 ma 5, 7 hold supply current (device selected, freq = max, v dd = max, v ddq = max, cke v dd 0.2 v, all inputs static at cmos levels) i dd1 e e 15 ma 6 notes: 1. lbo and zz pins have an internal pullup and will exhibit leakage currents of 5 m a. 2. reference ac operating conditions and characteristics for input and timing. 3. all addresses transition simultaneously low (lsb) then high (msb). 4. data states are all zero. 5. device in deselected mode as defined by the truth table. 6. cmos levels for i/os are v it v ss + 0.2 v or v ddq 0.2 v. cmos levels for other inputs are v in v ss + 0.2 v or v dd 0.2 v. 7. ttl levels for i/os are v it v il or v ih2 . ttl levels for other inputs are v in v il or v ih . capacitance (f = 1.0 mhz, t a = 0 to 70 c, periodically sampled rather than 100% tested) parameter symbol min typ max unit input capacitance c in e 4 5 pf input/output capacitance c i/o e 7 8 pf
mcm63z836 ? mcm63z918 15 motorola fast sram ac operating conditions and characteristics (v dd = 3.3 v 5%, t a = 0 to 70 c unless otherwise noted) input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . input pulse levels 0 to 3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 1 ns (20% to 80%) . . . . . . . . . . . . . . . . . . . . . . . . output timing reference level 1.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . output load see figure 6 unless otherwise noted . . . . . . . . . . . . . . r q ja under test tbd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . read/write cycle timing (see notes 1 and 2) p sbl mcm63z836225 mcm63z918225 225 mhz mcm63z836200 mcm63z918200 200 mhz mcm63z836166 mcm63z918166 166 mhz ui n parameter symbol min max min max min max unit notes cycle time t khkh 4.4 e 5 e 6 e ns clock high pulse width t khkl 1.7 e 2 e 2.4 e ns 3 clock low pulse width t klkh 1.7 e 2 e 2.4 e ns 3 clock access time t khqv e 2.6 e 3 e 3.6 ns output enable to output valid t glqv e 2.6 e 3 e 3.6 ns clock high to output active t khqx1 0.8 e 0.8 e 0.8 e ns 4, 5 output hold time t khqx 0.7 e 0.7 e 0.7 e ns 4 output enable to output active t glqx 0 e 0 e 0 e ns 4, 5 output disable to q highz t ghqz e 2.3 e 3 e 3.5 ns 4, 5 clock high to q highz t khqz 0.8 2.4 1 2.5 1 3 ns 4, 5 setup times: address adv data in write chip enable clock enable t adkh t lvkh t dvkh t wvkh t evkh t cvkh 1.3 1.3 1.2 1.3 1.3 1.3 e 1.3 1.3 1.2 1.3 1.3 1.3 e 1.3 1.3 1.2 1.3 1.3 1.3 e ns hold times: address adv data in write chip enable clock enable t khax t khlx t khdx t khwx t khex t khcx 0.5 e 0.5 e 0.5 e ns notes: 1. write is defined as any sbx and sw low. chip enable is defined as se1 low, se2 high, and sb3 low whenever adv is low. 2. all read and write cycle timings are referenced from ck or g . 3. in order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between data sheet parameters and actual system performance, fsram ac parametric specifications are always specified at v ddq /2. in some design exercises, it is desirable to evaluate timing using other reference levels. since the maximum test input edge rate is known and is given in the ac test conditions section of the data sheet as 1 v/ns, one can easily interpolate timing values to other reference levels. 4. this parameter is sampled and not 100% tested. 5. measured at 200 mv from steady state. output z 0 = 50 w r l = 50 w 1.5 v figure 6. ac test loads
mcm63z836 ? mcm63z918 16 motorola fast sram ck sa0 sax figure 7. ac timing parameter definitions t khkh t khkl t klkh t avkh t khax sw t wvkh t khwx sbx t wvkh t khwx e t evkh t khex adv t lvkh t khlx cke t cvkh t khcx g dq q dq t dvkh t khdx d dq t khqx1 q t khqz q t khqv t ghqz t glqx t glqv t khqx note: e is true if se1 = se3 = low and se2 = high. t glqx , t glqv , and t ghqz only apply if g is toggled. if g is tied low t khqx , t khqv , and t khqz apply.
mcm63z836 ? mcm63z918 17 motorola fast sram read/write cycles with hold and deselect cycles ck command ab c d e fg h ij rw hr w d rh wr dw rd q(a0) d(b0) q(c0) d(d0) q(e0) d(f0) q(g0) d(h0) q(i0) address code dq note: command code definitions are shown in truth table.
mcm63z836 ? mcm63z918 18 motorola fast sram read cycles (single, burst, and burst wraparound) ck command ab c rr bb b r bb bb address code dq q(a0) q(b0) q(b1) q(b2) q(b3) q(c0) q(c1) q(c2) q(c3) q(c0) note: command code definitions are shown in truth table.
mcm63z836 ? mcm63z918 19 motorola fast sram write cycles (single, burst, and burst wraparound) ck command ab c ww bb b w bb bb address code dq d(a0) d(b0) d(b1) d(b2) d(b3) d(c0) d(c1) d(c2) d(c3) d(c0) note: command code definitions are shown in truth table.
mcm63z836 ? mcm63z918 20 motorola fast sram read, write, read coherency with hold, and deselect cycles ck command ab c rw rw b r bd wh address code dq q(a0) d(b0) q(b0) d(c0) d(c1) q(c0) q(c1) d(d0) bc d de rr q(d0) q(e0) note: command code definitions are shown in truth table.
zz e k adv sleep mode timing sw g t zzqz note: t zzs t zzrec e low = se1 low, se2 high, se3 low. addr dq normal operation no reads or writes allowed (sw = h) in sleep mode no new reads or writes allowed normal operation i zz i (max) specifications will not be met if inputs toggle. zz i dd (sw = h) mcm63z836 ? mcm63z918 21 motorola fast sram
mcm63z836 ? mcm63z918 22 motorola fast sram application information sleep mode a sleep mode feature, the zz pin, has been implemented on the mcm63z836 and mcm63z918. it allows the system designer to place the ram in the lowest possible power condition by asserting zz. the sleep mode timing diagram shows the different modes of operation: normal operation, no read/write allowed, and sleep mode. each mode has its own set of constraints and conditions that are allowed. normal operation: all inputs must meet setup and hold times prior to sleep and t zzrec nanoseconds after re- covering from sleep. clock (k) must also meet cycle high and low times during these periods. two cycles prior to sleep, ini- tiation of either a read or write operation is not allowed. no read/write: during the period of time just prior to sleep and during recovery from sleep, the assertion of any write signal is not allowed. if a write operation occurs during these periods, the memory array may be corrupted. validity of data out from the ram can not be guaranteed immediately after zz is asserted (prior to being in sleep). sleep mode: the ram automatically deselects itself. the ram disconnects its internal clock buffer. the external clock may continue to run without impacting the rams sleep current (i zz ). all inputs are allowed to toggle e the ram will not be selected and perform any reads or writes. however, if inputs toggle, the i zz (max) specification will not be met. note: it is invalid to go from stop clock mode directly into sleep mode.
mcm63z836 ? mcm63z918 23 motorola fast sram serial boundary scan test access port operation overview the serial boundary scan test access port (tap) on this ram is designed to operate in a manner consistent with ieee standard 1149.11990 (commonly referred to as jtag), but does not implement all of the functions required for ieee 1149.1 compliance. certain functions have been modified or eliminated because their implementation places extra delays in the rams critical speed path. nevertheless, the ram supports the standard tap controller architecture (the tap controller is the state machine that controls the taps operation) and can be expected to function in a manner that does not conflict with the operation of devices with ieee standard 1149.1 compliant taps. the tap operates using a 3.3 v tolerant logic level signaling. disabling the test access port it is possible to use this device without utilizing the tap. to disable the tap controller without interfering with normal operation of the device, trst should be tied low and tck, tdi, and tms should be pulled through a resistor to 3.3 v. tdo should be left unconnected. tap dc operating characteristics (t a = 0 to 70 c, unless otherwise noted) parameter symbol min max unit notes input logic low v il 1 0.5 0.8 v input logic high v ih 1 2 3.6 v input leakage current i lkg e 10 m a 1 output logic low v ol 1 e 0.4 v 2 output logic high v oh 1 2.4 e v notes: 1. 0 v v in v ddq for all logic input pins. 2. for v ol = 0.4 v, 14 ma i ol 28 ma.
mcm63z836 ? mcm63z918 24 motorola fast sram tap ac operating conditions and characteristics (t a = 0 to 70 c, unless otherwise noted) ac test conditions parameter value unit input timing reference level 1.5 v input pulse levels 0 to 3.0 v input rise/fall time (20% to 80%) 1 v/ns output timing reference level 1.5 v output load (see figure 6 unless otherwise noted) e e tap controller timing parameter symbol min max unit notes tck cycle time t thth 60 e ns tck clock high time t th 25 e ns tck clock low time t tl 25 e ns tdo access time t tlqv 1 10 ns trst pulse width t tsrt 40 e ns setup times capture tdi tms t cs t dvth t mvth 5 5 5 e ns 1 hold times capture tdi tms t ch t thdx t thmx 13 14 14 e ns 1 note: 1. t cs and t ch define the minimum pauses in ram i/o transitions to assure accurate pad data capture. t thdx t tlqv t dvth t tlth t thmx t mvth tap controller timing diagram t thth test clock (tck) test mode select (tms) test data in (tdi) test data out (tdo) t thtl
mcm63z836 ? mcm63z918 25 motorola fast sram mcm63z836 boundary scan order bit no. signal name bump id 1 sa tbd 2 sa tbd 3 sa tbd 4 sa tbd 5 sa tbd 6 sa tbd 7 sa tbd 8 dqa tbd 9 dqa tbd 10 dqa tbd 11 dqa tbd 12 dqa tbd 13 dqa tbd 14 dqa tbd 15 dqa tbd 16 dqa tbd 17 zz tbd 18 dqb tbd 19 dqb tbd 20 dqb tbd 21 dqb tbd 22 dqb tbd 23 dqb tbd 24 dqb tbd 25 dqb tbd 26 dqb tbd 27 sa tbd 28 sa tbd 29 sa tbd 30 adv tbd 31 g tbd 32 cke tbd 33 sw tbd 34 ck tbd 35 se3 tbd bit no. signal name bump id 36 sba tbd 37 seb tbd 38 sbc tbd 39 sbd tbd 40 se2 tbd 41 se1 tbd 42 sa tbd 43 sa tbd 44 dqc tbd 45 dqc tbd 46 dqc tbd 47 dqc tbd 48 dqc tbd 49 dqc tbd 50 dqc tbd 51 dqc tbd 52 dqc tbd 53 v dd tbd 54 dqd tbd 55 dqd tbd 56 dqd tbd 57 dqd tbd 58 dqd tbd 59 dqd tbd 60 dqd tbd 61 dqd tbd 62 dqd tbd 63 lbo tbd 64 sa tbd 65 sa tbd 66 sa tbd 67 sa tbd 68 sa1 tbd 69 sa0 tbd
mcm63z836 ? mcm63z918 26 motorola fast sram mcm63z918 boundary scan order bit no. signal name bump id 1 sa tbd 2 sa tbd 3 sa tbd 4 sa tbd 5 sa tbd 6 sa tbd 7 sa tbd 8 dqa tbd 9 dqa tbd 10 dqa tbd 11 dqa tbd 12 zz tbd 13 dqa tbd 14 dqa tbd 15 dqa tbd 16 dqa tbd 17 dqa tbd 18 sa tbd 19 sa tbd 20 sa tbd 21 sa tbd 22 adv tbd 23 g tbd 24 cke tbd 25 sw tbd bit no. signal name bump id 26 ck tbd 27 se3 tbd 28 sba tbd 29 sbb tbd 30 sb2 tbd 31 se1 tbd 32 sa tbd 33 sa tbd 34 dqb tbd 35 dqb tbd 36 dqb tbd 37 dqb tbd 38 v dd tbd 39 dqb tbd 40 dqb tbd 41 dqb tbd 42 dqb tbd 43 dqb tbd 44 lbo tbd 45 sa tbd 46 sa tbd 47 sa tbd 48 sa tbd 49 sa1 tbd 50 sa0 tbd
mcm63z836 ? mcm63z918 27 motorola fast sram test access port pins tck e test clock (input) clocks all tap events. all inputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms e test mode select (input) the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input will not produce the same result as a logic 1 input level (not ieee 1149.1 compliant). tdi e test data in (input) the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is deter- mined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to figure 9). an undriven tdi pin will not pro- duce the same result as a logic 1 input level (not ieee 1149.1 compliant). tdo e test data out (output) output that is active depending on the state of the tap state machine (refer to figure 9). output changes in re- sponse to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo. trst e tap reset the trst is an asynchronous input that resets the tap controller and preloads the instruction register with the idcode command. this type of reset does not affect the operation of the system logic. the reset affects test logic only. test access port registers overview the various tap registers are selected (one at a time) via the sequences of 1s and 0s input to the tms pin as the tck is strobed. each of the taps registers are serial shift regis- ters that capture serial input data on the rising edge of tck and push serial data out on the subsequent falling edge of tck. when a register is selected, it is aplacedo between the tdi and tdo pins. instruction register the instruction register holds the instructions that are executed by the tap controller when it is moved into the run test/idle or the various data register states. the instructions are 3 bits long. the register can be loaded when it is placed between the tdi and tdo pins. the parallel outputs of the instruction register are automatically preloaded with the idcode instruction when trst is asserted or whenever the controller is placed in the testlogicreset state. the two least significant bits of the serial instruction register are loaded with a binary aoro pattern in the captureir state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed through the rams tap to another device in the scan chain with as little delay as possible. boundary scan register the boundary scan register is identical in length to the number of active input and i/o connections on the ram (not counting the tap pins). this also includes a number of place holder locations (always set to a logic 0) reserved for density upgrade address pins. there are a total of 67 bits in the case of the x36 device and 48 bits in the case of the x18 device. the boundary scan register, under the control of the tap controller, is loaded with the contents of the rams i/o ring when the controller is in capturedr state and then is placed between the tdi and tdo pins when the controller is moved to shiftdr state. the bump/bit scan order table describes which device bump connects to each boundary scan register location. the first column defines the bit's position in the boundary scan register. the shift register bit nearest tdo (i.e., first to be shifted out) is defined as bit 1. the second column is the name of the input or i/o at the bump and the third column is the bump number. identification (id) register the id register is a 32bit register that is loaded with a de- vice and vendor specific 32bit code when the controller is put in capturedr state with the idcode command loaded in the instruction register. the code is loaded from a 32bit onchip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when the controller is moved into shiftdr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. id register presence indicator bit no. 0 value 1 motorola jedec id code (compressed format, per ieee standard 1149.11990 bit no. 11 10 9 8 7 6 5 4 3 2 1 value 0 0 0 0 0 0 0 1 1 1 0 reserved for future use bit no. 17 16 15 14 13 12 value x x x x x x device width bit no. 22 21 20 19 18 256k x 36 0 0 1 0 0 512k x 18 0 0 0 1 1 device depth bit no. 27 26 25 24 23 256k x 36 0 0 1 1 0 512k x 18 0 0 1 1 1 revision number bit no. 31 30 29 28 value 0 0 0 0 figure 8. id register bit meanings
mcm63z836 ? mcm63z918 28 motorola fast sram tap controller instruction set overview there are two classes of instructions defined in the ieee standard 1149.11990; the standard (public) instructions and device specific (private) instructions. some public instructions, are mandatory for ieee 1149.1 compliance. optional public instructions must be implemented in pre- scribed ways. although the tap controller in this device follows the ieee 1149.1 conventions, it is not ieee 1149.1 compliant because some of the mandatory instructions are not fully imple- mented. the tap on this device may be used to monitor all input and i/o pads, but can not be used to load address, data, or control signals into the ram or to preload the i/o buffers. in other words, the device will not perform ieee 1149.1 extest, intest, or the preload portion of the sample/preload command. when the tap controller is placed in captureir state, the two least significant bits of the instruction register are loaded with 01. when the controller is moved to the shiftir state the instruction register is placed between tdi and tdo. in this state, the desired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions, the tap executes newly loaded instructions only when the controller is moved to updateir state. the tap instruction sets for this device are listed in the following tables. standard (public) instructions bypass the bypass instruction is loaded in the instruction regis- ter when the bypass register is placed between tdi and tdo. this occurs when the tap controller is moved to the shiftdr state. this allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. sample/preload sample/preload is an ieee 1149.1 mandatory public instruction. when the sample/preload instruction is loaded in the instruction register, moving the tap controller out of the capturedr state loads the data in the rams input and i/o buffers into the boundary scan register. because the ram clock(s) are independent from the tap clock (tck), it is possible for the tap to attempt to capture the i/o ring con- tents while the input buffers are in transition (i.e., in a metast- able state). although allowing the tap to sample metastable inputs will not harm the device, repeatable results can not be expected. ram input signals must be stabilized for long enough to meet the taps input data capture setup, plus hold time (t cs plus t ch ). the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan register. moving the controller to shiftdr state then places the boundary scan register between the tdi and tdo pins. be- cause the preload portion of the command is not im- plemented in this device, moving the controller to the updatedr state with the sample/preload instruction loaded in the instruction register has the same effect as the pausedr command. this functionality is not ieee 1149.1 compliant. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruction register, whatever length it may be in the device, is loaded with all logic 0s. extest is not implemented in this device. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capturedr mode and places the id register between the tdi and tdo pins in shiftdr mode. the idcode instruction is the default instruction loaded in at trst assertion and any time the con- troller is placed in the testlogicreset state. the device specific (public) instruction samplez if the highz instruction is loaded in the instruction regis- ter, all dq pins are forced to an inactive drive state (highz) and the bypass register is connected between tdi and tdo when the tap controller is moved to the shiftdr state. the device specific (private) instruction no op do not use these instructions; they are reserved for future use.
mcm63z836 ? mcm63z918 29 motorola fast sram standard and device specific (public) instruction codes instruction code* description idcode 001** preloads id register and places it between tdi and tdo. does not affect ram operation. highz 010 captures i/o ring contents. places the bypass register between tdi and tdo. forces all dq pins to highz. not ieee 1149.1 compliant. bypass 011 places bypass register between tdi and tdo. does not affect ram operation. not ieee 1149.1 compliant. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. does not affect ram operation. does not implement ieee 1149.1 preload function. not ieee 1149.1 compliant. * instruction codes expressed in binary, msb on left, lsb on right. ** default instruction automatically loaded when trst asserted or in testlogicreset state. standard (private) instruction codes instruction code* description no op 000 do not use these instructions; they are reserved for future use. no op 101 do not use these instructions; they are reserved for future use. no op 110 do not use these instructions; they are reserved for future use. no op 111 do not use these instructions; they are reserved for future use. * instruction codes expressed in binary, msb on left, lsb on right. capturedr exit1dr exit2dr updatedr captureir exit1ir exit2ir updateir shiftir pauseir pausedr testlogic reset runtest/ idle select drscan select irscan 1 0 1 1 1 1 1 1 1 11 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 note: the value adjacent to each state transition represents the signal present at tms at the rising edge of tck. 0 figure 9. tap controller state diagram 0 shiftdr
mcm63z836 ? mcm63z918 30 motorola fast sram mcm 63z918 xx x x motorola memory prefix part number full part numbers e mcm63z836tq225 mcm63z836tq200 mcm63z836tq166 MCM63Z836TQ225R mcm63z836tq200r mcm63z836tq166r mcm63z918tq225 mcm63z918tq200 mcm63z918tq166 mcm63z918tq225r mcm63z918tq200r mcm63z918tq166r mcm63z836zp225 mcm63z836zp200 mcm63z836zp166 mcm63z836zp225r mcm63z836zp200r mcm63z836zp166r mcm63z918zp225 mcm63z918zp200 mcm63z918zp166 mcm63z918zp225r mcm63z918zp200r mcm63z918zp166r package (tq = tqfp, zp = pbga) blank = trays, r = tape and reel speed (225 = 225 mhz, 200 = 200 mhz, 166 = 166 mhz) ordering information (order by full part number) 63z836
mcm63z836 ? mcm63z918 31 motorola fast sram tq package tqfp case 983a01 package dimensions dim min max min max inches millimeters a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 b1 0.22 0.33 0.009 0.013 c 0.09 0.20 0.004 0.008 c1 0.09 0.16 0.004 0.006 d 22.00 bsc 0.866 bsc e 16.00 bsc 0.630 bsc e1 14.00 bsc 0.551 bsc e 0.65 bsc 0.026 bsc l 0.45 0.75 0.018 0.030 l1 1.00 ref 0.039 ref l2 0.50 ref s 0.20 0.008 r1 0.08 0.003 r2 0.08 0.20 0.003 0.008 0 7 0 7 0 0 11 13 11 13 11 13 11 13 1 2 3 d1 20.00 bsc 0.787 bsc 0.020 ref notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums a, b and d to be determined at datum plane h. 5. dimensions d and e to be determined at seating plane c. 6. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions d1 and b1 do include mold mismatch and are determined at datum plane h. 7. dimension b does not include dambar protrusion. dambar protrusion shall not cause the b dimension to exceed 0.45 (0.018). ab 0.20 (0.008) h e d ab 0.20 (0.008) c d ab 0.20 (0.008) c d 0.10 (0.004) c 0.25 (0.010) s 0.05 (0.002) s ab m 0.13 (0.005) d s c e/2 d/2 e e1 d1 d d1/2 e1/2 e/2 4x 2x 30 tips 2x 20 tips d b a c h 1 3 2 100 81 80 51 50 31 30 1 plating section bb c1 c b b1 ???? ???? ???? base metal a seating plane view ab s view ab a2 a1 r1 l2 l l1 r2 gage plane x view y b b x=a, b, or d
mcm63z836 ? mcm63z918 32 motorola fast sram zp package 7 x 17 bump pbga case 99902 a b c d e f g h j k l m n p r t u d2 e2 4x 16x 119x top view bottom view side view d 0.20 6x e e 7654321 b 0.35 a c e 0.25 a 0.20 a a seating plane a a1 a2 a3 m 0.3 c a b m 0.15 a d1 e1 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. all dimensions in millimeters. 3. dimension b is the maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane, is defined by the spherical crowns of the solder balls. dim min max millimeters a 2.40 a1 0.50 0.70 a2 1.30 1.70 a3 0.80 1.00 d 22.00 bsc d1 20.32 bsc d2 19.40 19.60 e 14.00 bsc e1 7.62 bsc e2 11.90 12.10 b 0.60 0.90 e 1.27 bsc b motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed: motorola literature distribution; japan : motorola japan ltd.; spd, strategic planning office, 141, p.o. box 5405, denver, colorado, 80217. 1-303-675-2140 or 1-800-441-2447 4-32-1 nishi-gotanda, shinagawa-ku, tokyo, japan. 81-3-5487-8488 mfax ? : rmfax0@email.sps.mot.com t ouchtone 1-602-244-6609 asia / pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, motorola fax back system us & c anada only 1-800-774-1848 2 dai king street, tai po industrial estate, tao po, n.t., hong kong. http ://sps.motorola.com /mfax / 852-26668334 home page : http ://motorola.com/sps / customer focus center: 1-800-521-6274 mcm63z836/d ?

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